Chinese Academy of Sciences releases domestic open-source high-performance RISC-V processor "Xiangshan"

On the morning of June 22-25, the first RISC-V China Summit was held at ShanghaiTech University. At this conference, Bao Yungang, a professor at the University of Chinese Academy of Sciences and a researcher at the Institute of Computing Technology of the Chinese Academy of Sciences, released the homemade open-source high-performance RISC-V processor "Xiangshan".

According to Bao Yungangs introduction, Xiangshan is an open-source RISC-V processor core, which was developed with the support of the Chinese Academy of Sciences Computing Institute and Pengcheng Laboratory through the China Open Command Ecology (RISC-V) Alliance and industry companies. . Beijing Microcore Technology Co., Ltd. provided industry experience and jointly completed the structural design and physical design.

The Xiangshan processor is implemented based on the Chisel hardware design language and supports the RV64GC instruction set. During the development of the Xiangshan processor, the team used a large number of open-source tools, including Chisel, Verilator, etc., to implement basic tools for processor development such as differential verification, simulation snapshots, and RISC-V checkpoints, and established a set of The agile development process of the processor front-end based on open source tools including design, implementation, verification, etc.

It is worth mentioning that the second phase of the Xiangshan processor will be jointly developed with Microcore Technology, ByteDance, ESWIN, and USi Technology.

Bao Yungang said that the architecture code name of the Xiangshan processor will be named after the lake: the first version of the architecture code is "Yanqi Lake", the second version of the architecture code is "South Lake", the third, fourth, and subsequent versions will still be named after the lake. Name the lake (Lake X, Lake Y...).

The first version of the architecture "Yanqi Lake" is an out-of-order processor core with 11 stages of the pipeline, 6 launches, and 4 memory access components. The code warehouse of "Yanqi Lake" will be established in June 2020, and the RTL code will be completed in April 2021. "Yanqi Lake" is planned to be taped out in July based on TSMC's 28nm process. The current frequency is 1.3GHz, and the SPEC CPU2006 score is estimated to be around 7 cents/GHz. This product is mainly against ARM A72 and A73.

The second version of the architecture "South Lake" is planned to be taped out by the end of this year. It will use SMIC's 14nm process with a target frequency of 2GHz and a SPEC CPU score of 10 cents/GHz.

According to the introduction, the performance of "Nanhu" has been greatly improved compared with the first version of "Yanqi Lake", which is close to the 11.08/GHz of i9-10900K, and supports dual-channel DDR memory and more functions such as PCIe, USB, HDMI and so on. The "Yanqi Lake" architecture is comparable to some ARM high-end processor cores in launch width, but it has not yet been fully optimized, so there is still a big gap in actual performance. He hopes that in the future, through continuous iterative optimization of the new architecture from "Yanqi Lake" to "South Lake" to "X Lake" and "Y Lake", the performance of the ARM A76 level can be reached.

Bao Yungang hoped that "Fragrant Mountain" could survive for 30 years, and agreed to get together again after 30 years. In addition, Xiangshan will maintain the iterative optimization frequency of the new generation architecture for half a year, tape it out twice a year and verify the new architecture and new functions, and establish a standardized open-source community management mechanism. Netizens commented: First of all, the current challenge of RISC V is ARM, and the team of teacher Yungang Bao initiated an open-source chip project. The goal is to be an open-source chip community like Linux. This development process There are many breakthroughs in the development language. The development language uses the chisel language instead of the traditional Verilog. At the same time, a lot of tools have been made. Secondly, the differential verification framework is also one."

It is believed that after more giants enter the RISC-V field, the ecology of RISC-V will gradually be improved, and the Xiangshan processor is an important step.